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<p>MIPI DSI Rx Subsystem configuration structure.  
 <a href="struct_x_dsi2_rx_ss___config.html#details">More...</a></p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a89d38ccb74c8a7f20fba792149999d9c"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#a89d38ccb74c8a7f20fba792149999d9c">BaseAddr</a></td></tr>
<tr class="memdesc:a89d38ccb74c8a7f20fba792149999d9c"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">    BaseAddress is the physical
</pre><p> base address of the subsystem address range  <a href="#a89d38ccb74c8a7f20fba792149999d9c">More...</a><br/></td></tr>
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<tr class="memitem:a05ffa17e949fc526b6e804f84f004a0c"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#a05ffa17e949fc526b6e804f84f004a0c">HighAddr</a></td></tr>
<tr class="memdesc:a05ffa17e949fc526b6e804f84f004a0c"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">    HighAddress is the physical
</pre><p> MAX address of the subsystem address range  <a href="#a05ffa17e949fc526b6e804f84f004a0c">More...</a><br/></td></tr>
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<tr class="memitem:a9d5d63355188543a83d426ffe6f2e720"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#a9d5d63355188543a83d426ffe6f2e720">DataType</a></td></tr>
<tr class="memdesc:a9d5d63355188543a83d426ffe6f2e720"><td class="mdescLeft">&#160;</td><td class="mdescRight">RGB type.  <a href="#a9d5d63355188543a83d426ffe6f2e720">More...</a><br/></td></tr>
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<tr class="memitem:a32b721fb312e0477e645127b162c9968"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#a32b721fb312e0477e645127b162c9968">DsiPixel</a></td></tr>
<tr class="memdesc:a32b721fb312e0477e645127b162c9968"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pixels per beat received on input stream.  <a href="#a32b721fb312e0477e645127b162c9968">More...</a><br/></td></tr>
<tr class="separator:a32b721fb312e0477e645127b162c9968"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a75513e422081486a97e0ef1e3e7ac136"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#a75513e422081486a97e0ef1e3e7ac136">DphyLinerate</a></td></tr>
<tr class="memdesc:a75513e422081486a97e0ef1e3e7ac136"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPHY line rate.  <a href="#a75513e422081486a97e0ef1e3e7ac136">More...</a><br/></td></tr>
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<tr class="memitem:a990e7b739eaf7b9cca5d69346756afc9"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#a990e7b739eaf7b9cca5d69346756afc9">IsDphyRegIntfcPresent</a></td></tr>
<tr class="memdesc:a990e7b739eaf7b9cca5d69346756afc9"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">Flag for DPHY register
</pre><p> interface presence  <a href="#a990e7b739eaf7b9cca5d69346756afc9">More...</a><br/></td></tr>
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<tr class="memitem:aeb9967254fd9e94cc7fa5973eb9ffb41"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dsi2_rx_ss_sub_cores.html">Dsi2RxSsSubCores</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#aeb9967254fd9e94cc7fa5973eb9ffb41">DphyInfo</a></td></tr>
<tr class="memdesc:aeb9967254fd9e94cc7fa5973eb9ffb41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#aeb9967254fd9e94cc7fa5973eb9ffb41">More...</a><br/></td></tr>
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<tr class="memitem:ae5bda84d926823f372d40496afea493c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dsi2_rx_ss_sub_cores.html">Dsi2RxSsSubCores</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi2_rx_ss___config.html#ae5bda84d926823f372d40496afea493c">Dsi2RxInfo</a></td></tr>
<tr class="memdesc:ae5bda84d926823f372d40496afea493c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ae5bda84d926823f372d40496afea493c">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>MIPI DSI Rx Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
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<p><pre class="fragment">    BaseAddress is the physical
</pre><p> base address of the subsystem address range </p>

<p>Referenced by <a class="el" href="xdsi2rxss__selftest__example_8c.html#aca3784ffa88ce005208db9acd21dc07c">Dsi2RxSs_SelfTestExample()</a>, and <a class="el" href="group__dsirxss.html#gacf02fba1186dd59ea301c448f21c6cce">XDsi2RxSs_CfgInitialize()</a>.</p>

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          <td class="memname">u8 XDsi2RxSs_Config::DataType</td>
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<p>RGB type. </p>

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          <td class="memname"><a class="el" href="struct_dsi2_rx_ss_sub_cores.html">Dsi2RxSsSubCores</a> XDsi2RxSs_Config::DphyInfo</td>
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<p>Sub-core instance configuration. </p>

<p>Referenced by <a class="el" href="group__dsirxss.html#ga9ddf0047db648a70d3a504fad94af7e1">XDsi2RxSs_ReportCoreInfo()</a>.</p>

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          <td class="memname">u32 XDsi2RxSs_Config::DphyLinerate</td>
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<p>DPHY line rate. </p>

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          <td class="memname"><a class="el" href="struct_dsi2_rx_ss_sub_cores.html">Dsi2RxSsSubCores</a> XDsi2RxSs_Config::Dsi2RxInfo</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname">u8 XDsi2RxSs_Config::DsiPixel</td>
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<p>Pixels per beat received on input stream. </p>

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<p><pre class="fragment">    HighAddress is the physical
</pre><p> MAX address of the subsystem address range </p>

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          <td class="memname">u32 XDsi2RxSs_Config::IsDphyRegIntfcPresent</td>
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<p><pre class="fragment">Flag for DPHY register
</pre><p> interface presence </p>

<p>Referenced by <a class="el" href="group__dsirxss.html#ga911fad210453719e9310c3b138096985">XDsi2RxSs_Reset()</a>.</p>

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